Next-Generation Submodule Technology for MMC

• Its scalability
• No need for passive filters
• Low di/dt of the arm currents
• Low switching frequency and
• Direct and fast control of the AC- and DC-side.

In previous projects, MMC have basically been equipped with Half-Bridge Submodules due to the minimum expenditure of semiconductors and therefore low losses. The disadvantage of Half-Bridge Submodules on the other hand is no possibility for electronic DC-current limitation at converter level (regarding unipolar terminal voltage) and high volume submodule capacitors.

Future requirements for MMC at system level are therefore the:

• Reduction of submodule capacitor volume
• Applying submodule topologies with bipolar terminal voltage to enable DC-current limitation and cut-off by the MMC itself (what results in the redundancy of DC circuit breakers) and
• Enabling electronic protection of submodules against explosion

The future requirements should concurrently not lead to increased converter losses.

The Double-Zero Submodule (DZ-SM)

By introducing a controllable DC-capacitor – realized by a reverse conducting SiC-FET – a novel control scheme becomes possible, enabling reduced on-state losses and reduced switching losses. In addition, a double submodule circuit (DZ-DC-SM) can be realized by external connection of two single DZ-SM.

Fig. 1: Double-Zero submodule (DZ-SM) and Double-Connection of two DZ-SM (DZ-DC-SM)

The features of this novel topology in Double-Connection are:

• Reduced on-state losses
• Reduced capacitor size
• Lossless capacitor balancing
• Electronic protection against explosion and it is
• Well adapted for SiC-FET.

The most promising submodules are investigated, in order to analyze the individual on-state power loss of the different semiconductors:

1. Series connection of two Full-Bridge submodules (FB-SM)
2. Series connection of two Double-Zero submodules (DZ-SM)
3. Double Zero submodule in double-connection (DZ-DC-SM).

The left bar graphs in B) and C) are depicting submodules as a mixture of Si-HV-IGBT and SiC-FET semiconductor devices as a next technological step, where a fully Si-HV-IGBT-version of the conventional FB-SM is utilized as a reference in A). By comparison, fully SiC-FET equipped submodules are presented in the right bar graphs.
It can be noted, that the on-state losses of the Double-Zero submodule (B)) can be significantly reduced, where the full potential of loss reduction will be achieved with a fully SiC-FET equipped submodule. In the case of the double-connection (C)), further 25% loss reduction can be achieved –cutting the total on-state loss in half compared to the conventional Full-Bridge submodule topology.

Fig. 2: Normalized total power losses per submodule in a typ. HVDC-MMC application