Weber, J., Fung, R., Wong, R., Wolf, H., Gieser, H., Maurer, L.: "Stress Current Slew Rate Sensitivity of an Ultra-High-Speed Interface IC", IEEE Transactions on Device and Materials Reliability, Pages: 1 -1, 2019

Ammer, M., Rupp, A., Glaser, U., Cao, Y., Sauter, M., Maurer, L.: "Application Example of a Novel Methodology to Generate IC Models for System ESD and Electrical Stress Simulation out of the Design Data", 41st Annual EOS/ESD Symposium (EOS/ESD), 2019

Ammer, M., Miropolskiy, S., Rupp, A., zur Nieden, F., Sauter, M., Maurer, L.: "Characterizing and Modelling Common Mode Inductors at high Current Levels for System ESD Simulations", 41st Annual EOS/ESD Symposium (EOS/ESD), 2019

Bora, P., Borggreve, D., Vanselow, F., Isa, E., Maurer, L.: "A low power Sigma-Delta Modulator in an advanced 22 nm FD SOI CMOS Process for sensor applications", 13th International Conference and Exhibition on Integration Issues of Miniaturized Systems, Pages: 1 - 7, 2019

Ammer, M., Cao, Y., Rupp, A., Sauter, M., Maurer, L.: "Bringing the SEED Approach to the Next Level: Generating IC Models for System ESD and Electrical Stress Simulation out of Design Data", IEEE Transactions on Electromagnietic Compatibility, Pages: 1 -11, 2019

Koch, S., Orr, B., Gossner, H., Gieser, H., Maurer, L.: "Identification of  Soft Failure Mechanisms Triggered by ESD Stress on a Pawered USB 3.0 Interface", IEEE Transactions on Electromagnetic Compatibility, Pages: 20 - 28, 2019